This invention relates to a dynamic semiconductor memory device.
Already known is a dynamic type semiconductor memory device using a MOS transistor and arranged as shown in FIG. 1. This conventional semiconductor memory device comprises a memory section A mounted on a P-type semiconductor substrate 10 biased to a negative potential V.sub.BB of, for example, -2 to -3 volts and a peripheral circuit B. A memory cell Q1 included in the memory section A comprises a transfer gate 18 formed of a gate electrode 12, gate insulation layer 14, and source or drain region 16; and a MOS capacitor 26 formed of a gate electrode 20, gate insulation layer 22 and inversion region 24. The peripheral circuit B consists of an N channel MOS transistor Q2 formed of a source region 28, a drain region 30 constructed by diffusing an N-type impurity at high concentration, and a gate electrode 34 mounted above the surface of the semiconductor substrate 10 with a thin insulation layer 32 interposed therebetween. With the conventional dynamic semiconductor memory device, data representing the presence or absence of an electron in the inversion region 24 is stored. However, this conventional memory device has the drawback that where a hot electron 36 released from the MOS transistor Q2 constituting the peripheral circuit B diffuses through the P-type semiconductor substrate 10 up to the memory cell Q1, then data stored in the inversion region 24 is disturbed.
The occurrence of such hot electron 36 tends to be prominent particularly in a densely integrated MOS field effect transistor. With a large-scale integrated semiconductor memory device, therefore, the generation of a hot electron presents a great problem.